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july 2012 ? 2009 fairchild semiconductor corporation www.fairchildsemi.com fxla104 ? rev. 1.0.9 fxla104 ? low-voltage dual-suppl y 4-bit voltage translator fxla104 low-voltage dual-supply 4-bit voltage translator with configurable voltage supplies and signal levels, 3-state outputs, and auto direction sensing features ? bi-directional interface between two levels: from 1.1v to 3.6v ? fully configurable: inputs and outputs track v cc ? non-preferential power-up; either v cc may be powered up first ? outputs switch to 3-state if either v cc is at gnd ? power-off protection ? bus-hold on data inputs eliminates the need for pull-up resistors; do not use pull-up resistors on a or b ports ? control input (/oe) referenced to v cca voltage ? available in 16-terminal umlp (1.8mm x 2.6mm) and 12-terminal, quad umlp, 1.8 x 1.8mm packages ? direction control not necessary ? 100mbps throughput when translating between 1.8v and 2.5v ? esd protection exceeds: - 8kv hbm (per jesd22-a114 & mil std 883e 3015.7) - 2kv cdm (per esd stm 5.3) applications ? cell phone, pda, digital camera, portable gps description the fxla104 is a configurable dual-voltage supply translator for both uni-directional and bi-directional voltage translation between two logic levels. the device allows translation between voltages as high as 3.6v to as low as 1.1v. the a port tracks the v cca level and the b port tracks the v ccb level. this allows for bi-directional voltage translation over a vari ety of voltage levels: 1.2v, 1.5v, 1.8v, 2.5v, and 3.3v. the device remains in three-state as long as either v cc =0v, allowing either v cc to be powered up first. internal power-down control circuits place the device in 3-state if either v cc is removed. the /oe input, when high, disables both the a and b ports by placing them in a 3-state condition. the /oe input is supplied by v cca . the fxla104 supports bi-directional translation without the need for a direction contro l pin. the two ports of the device have auto-direction sense capability. either port may sense an input signal and transfer it as an output signal to the other port. ordering information part number operating temperature range top mark package packing method fxla104umx -40 to 85c xj 16-terminal umlp 1.8 x 2.6mm package 5k units tape and reel fxla104um12x xj 12-terminal, quad umlp, 1.8 x 1.8mm package
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fxla104 ? rev. 1.0.9 2 fxla104 ? low-voltage dual-suppl y 4-bit voltage translator pin configuration figure 1. 16-pin umlp (top through view) f igure 2. 12-pin umlp (top through view) pin definitions 16 pin # 12 pin # name description 1 3 a0 a-side inputs or 3-state outputs 2 4 a1 a-side inputs or 3-state outputs 3 5 a2 a-side inputs or 3-state outputs 4 6 a3 a-side inputs or 3-state outputs 5 nc no connect 6,7 7 gnd ground 8 8 /oe output enable input 9 9 b3 b-side inputs or 3-state outputs 10 10 b2 b-side inputs or 3-state outputs 11 11 b1 b-side inputs or 3-state outputs 12 12 b0 b-side inputs or 3-state outputs 13 1 v ccb b-side power supply 14,15 nc no connect 16 2 v cca a-side power supply v ccb nc nc v cca a 0 a 1 a 2 a 3 nc gnd gnd /oe b3 b2 b1 b0 12 11 1 0 9 8 7 6 5 4 3 2 1 16 15 14 13
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fxla104 ? rev. 1.0.9 3 fxla104 ? low-voltage dual-suppl y 4-bit voltage translator functional diagram figure 3. functional diagram function table control outputs /oe low logic level normal operation high logic level 3-state
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fxla104 ? rev. 1.0.9 4 fxla104 ? low-voltage dual-suppl y 4-bit voltage translator absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and st ressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recomm ended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter conditions min. max. unit v cc supply voltage v cca -0.5 4.6 v v ccb -0.5 4.6 v i dc input voltage i/o ports a and b -0.5 4.6 v control input (/oe) -0.5 4.6 v o output voltage (2) output 3-state -0.5 4.6 v output active (a n ) -0.5 v cca +0.5 output active (b n ) -0.5 v ccb +0.5 i ik dc input diode current v in <0v -50 ma i ok dc output diode current v o <0v -50 ma v o >v cc +50 i oh /i ol dc output source/sink current -50 +50 ma i cc dc v cc or ground current (per supply pin) 100 ma t stg storage temperature range -65 +150 c p d power dissipation 17 mw esd electrostatic discharge capability human body model (per jesd22- a114 & mil std 883e 3015.7) 8 kv charged device model (per esd stm 5.3) 2 notes: 1. i o absolute maximum ratings must be observed. 2. all unused inputs and input/outputs must be held at v cci or gnd. recommended operating conditions the recommended operating conditions table defines th e conditions for actual device operation. recommended operating conditions are specified to en sure optimal performance to the datash eet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter conditions min. max. unit v cc power supply operating v cca or v ccb 1.1 3.6 v v in input voltage ports a and b 0 3.6 v control input (/oe) 0 v cca v t a operating temperature, free air -40 +85 c dt/dv minimum input edge rate v cca/b = 1.1 to 3.6v 10 ns/v ja thermal resistance: junction-to-ambient umlp-16 315 c/w umlp-12 300 jc thermal resistance: junction-to-case umlp-16 155 c/w umlp-12 165
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fxla104 ? rev. 1.0.9 5 fxla104 ? low-voltage dual-suppl y 4-bit voltage translator power-up/power-down sequence fxl translators offer an advantage in that either v cc may be powered up first. this benefit derives from the chip design. when either v cc is at 0v, outputs are in a high-impedance state. the control input (/oe) is designed to track the v cca supply. a pull-up resistor tying /oe to v cca should be used to ensure that bus contention, excessive currents, or oscillations do not occur during power-up or power-down. the size of the pull-up resistor is based upon the current-sinking capability of the device driving the /oe pin. the recommended power-up sequence is: 1. apply power to the first v cc . 2. apply power to the second v cc . 3. drive the /oe input low to enable the device. the recommended power-down sequence is: 1. drive /oe input high to disable the device. 2. remove power from either v cc . 3. remove power from other v cc. pull-up/pull-down resistors do not use pull-up or pull-down resistors . this device has bus-hold circuits: pull-up or pull-down resistors are not recommended because they interfere with the output state. the current th rough these resistors may exceed the hold drive, i i(hold) and/or i i(od) bus-hold currents, resulting in dat a transition and/or auto- direction sensing failures. the bus-hold feature eliminates the need for extra resistors.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fxla104 ? rev. 1.0.9 6 fxla104 ? low-voltage dual-suppl y 4-bit voltage translator dc electrical characteristics t a =-40 to 85c symbol parameter conditions v cca (v) v ccb (v) min. typ. max. units v iha high-level input voltage data inputs a n control pin /oe 2.70 to 3.60 1.10 to 3.60 2.00 v 2.30 to 2.70 1.60 1.65 to 2.30 .65xv cca 1.40 to 1.65 .65xv cca 1.10 to 1.40 .90xv cca v ihb data inputs b n 1.10 to 3.60 2.70 to 3.60 2.00 v 2.30 to 2.70 1.60 1.65 to 2.30 .65xv ccb 1.40 to 1.65 .65xv ccb 1.10 to 1.40 .90xv ccb v ila low-level input voltage data inputs a n control pin /oe 2.70 to 3.60 1.10 to 3.60 .80 v 2.30 to 2.70 .70 1.65 to 2.30 .35xv cca 1.40 to 1.65 .35xv cca 1.10 to 1.40 .10xv cca v ilb data inputs b n 1.10 to 3.60 2.70 to 3.60 .80 v 2.30 to 2.70 .70 1.65 to 2.30 .35xv ccb 1.40 to 1.65 .35xv ccb 1.10 to 1.40 .10xv ccb v oha high-level output voltage (3) i oh =-4a 1.10 to 3.60 1.10 to 3.60 v cca -.4 v v ohb i oh =-4a 1.10 to 3.60 1.10 to 3.60 v ccb - .4 v ola low-level output voltage (3) i ol =4a 1.10 to 3.60 1.10 to 3.60 .4 v v olb i ol =4a 1.10 to 3.60 1.10 to 3.60 .4 i i(hold) bus-hold input minimum drive current v in =0.8v 3.00 3.00 75.0 a v in =2.0v 3.00 3.00 -75.0 v in =0.7v 2.30 2.30 45.0 v in =1.6v 2.30 2.30 -45.0 v in =0.57v 1.65 1.65 25.0 v in =1.07v 1.65 1.65 -25.0 v in =0.49v 1.40 1.40 11.0 v in =0.91v 1.40 1.40 -11.0 v in =0.11v 1.10 1.10 4.0 v in =0.99v 1.10 1.10 -4.0 note: 3. this is the output voltage for static conditions. dynamic drive specific ations are given in the dynamic output electrical characteristics table. continued on following page?
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fxla104 ? rev. 1.0.9 7 fxla104 ? low-voltage dual-suppl y 4-bit voltage translator dc electrical characteristics (continued) t a =-40 to 85c. symbol parameter conditions v cca (v) v ccb (v) min. max. units i i(odh) bus-hold input overdrive high current (4) data inputs a n , b n 3.60 3.60 450.0 a 2.70 2.70 300.0 1.95 1.95 200.0 1.60 1.60 120.0 1.40 1.40 80.0 i i(odl) bus-hold input overdrive low current (5) data inputs a n , b n 3.60 3.60 -450.0 a 2.70 2.70 -300.0 1.95 1.95 -200.0 1.60 1.60 -120.0 1.40 1.40 -80.0 i i input leakage current control inputs /oe, v i =v cca or gnd 1.10 to 3.60 3.60 1.0 a i off power-off leakage current a n v o =0v to 3.6v 0 3.60 2.0 a b n v o =0v to 3.6v 3.60 0 2.0 i oz 3-state output leakage a n , b n v o =0v or 3.6v, /oe=v ih 3.60 3.60 5.0 a a n v o =0v or 3.6v, /oe=gnd 3.60 0 5.0 b n v o =0v or 3.6v, /oe=gnd 0 3.60 5.0 i cca/b quiescent supply current (6, 7) v i =v cci or gnd; i o =0, /oe=gnd 1.10 to 3.60 1.10 to 3.60 10.0 a i ccz v i =v cci or gnd; i o =0, /oe=v ih 1.10 to 3.60 1.10 to 3.60 10.0 a i cca quiescent supply current v i =v ccb or gnd; i o =0 b-to-a direction, /oe=gnd 0 1.10 to 3.60 -10.0 a v i =v cca or gnd; i o =0 a-to-b direction 1.10 to 3.60 0 10.0 i ccb v i =v cca or gnd; i o =0, a-to-b direction, /oe=gnd 1.10 to 3.60 0 -10.0 a v i =v ccb or gnd; i o =0 b-to-a direction 0 1.10 to 3.60 10.0 notes: 4. an external drive must source at least the specified current to switch low-to-high. 5. an external drive must source at least the specified current to switch high-to-low. 6. v cci is the v cc associated with the input side. 7. reflects current per supply, v cca or v ccb .
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fxla104 ? rev. 1.0.9 8 fxla104 ? low-voltage dual-suppl y 4-bit voltage translator dynamic output electr ical characteristic a port (a n ) output load: c l =15pf, r l m (c i/o =4pf), t a =-40 to 85c symbol parameter v cca =3.0v to 3.6v v cca =2.3v to 2.7v v cca =1.65v to 1.95v v cca =1.4v to 1.6v v cca =1.1v to 1.3v units typ. max. typ. max. typ. max typ. max. typ. t rise output rise time a port (9) 3.0 3.5 4.0 5.0 7.5 ns t fall output fall time a port (10) 3.0 3.5 4.0 5.0 7.5 ns i ohd dynamic output current high (9) -11.4 -7.5 -4.7 -3.2 -1.7 ma i old dynamic output current low (10) +11.4 +7.5 +4.7 +3.2 +1.7 ma b port (b n ) output load: c l =15pf, r l m (c i/o =5pf), t a =-40 to 85c symbol parameter v ccb =3.0v to 3.6v v ccb =2.3v to 2.7v v ccb =1.65v to 1.95v v ccb =1.4v to 1.6v v ccb =1.1v to 1.3v units typ. max. typ. max. typ. max typ. max. typ. t rise output rise time b port (9) 3.0 3.5 4.0 5.0 7.5 ns t fall output fall time b port (10) 3.0 3.5 4.0 5.0 7.5 ns i ohd dynamic output current high (9) -12.0 -7.9 -5.0 -3.4 -1.8 ma i old dynamic output current low (10) +12.0 +7.9 +5.0 +3.4 +1.8 ma notes: 8. dynamic output characteristic s are guaranteed, but not tested. 9. see figure 8 . 10. see figure 9.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fxla104 ? rev. 1.0.9 9 fxla104 ? low-voltage dual-suppl y 4-bit voltage translator ac characteristics v cca = 3.0v to 3.6v, t a =-40 to 85c symbol parameter v ccb =3.0v to 3.6v v ccb =2.3v to 2.7v v ccb =1.65v to 1.95v v ccb =1.4v to 1.6v v ccb =1.1v to 1.3v units min. max. min. max. min. max min. max. typ. t plh ,t phl a to b 0.2 4.0 0.3 4.2 0.5 5.4 0.6 6.8 6.9 ns b to a 0.2 4.0 0.2 4.1 0.3 5.0 0.5 6.0 4.5 ns t pzl ,t pzh /oe to a, /oe to b 1.7 1.7 1.7 1.7 1.7 s t skew a port, b port (11) 0.5 0.5 0.5 1.0 1.0 ns v cca = 2.3v to 2.7v, t a =-40 to 85c symbol parameter v ccb =3.0v to 3.6v v ccb =2.3v to 2.7v v ccb =1.65v to 1.95v v ccb =1.4v to 1.6v v ccb =1.1v to 1.3v units min. max. min. max. min. max min. max. typ. t plh ,t phl a to b 0.2 4.1 0.4 4.5 0.5 5.6 0.8 6.9 7.0 ns b to a 0.3 4.2 0.4 4.5 0.5 5.5 0.5 6.5 4.8 ns t pzl ,t pzh /oe to a, /oe to b 1.7 1.7 1.7 1.7 1.7 s t skew a port, b port (11) 0.5 0.5 0.5 1.0 1.0 ns v cca = 1.65v to 1.95v, t a =-40 to 85c symbol parameter v ccb =3.0v to 3.6v v ccb =2.3v to 2.7v v ccb =1.65v to 1.95v v ccb =1.4v to 1.6v v ccb =1.1v to 1.3v units min. max. min. max. min. max min. max. typ. t plh ,t phl a to b 0.3 5.0 0.5 5.5 0.8 6.7 0.9 7.5 7.5 ns b to a 0.5 5.4 0.5 5.6 0.8 6.7 1.0 7.0 5.4 ns t pzl ,t pzh /oe to a, /oe to b 1.7 1.7 1.7 1.7 1.7 s t skew a port, b port (11) 0.5 0.5 0.5 1.0 1.0 ns note: 11. skew is the variation of propagat ion delay between output signals and applies only to output signals on the same port (a n or b n ) and switching with the same polarity (low-to-high or high-to-low) (see figure 11). skew is guaranteed, but not tested.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fxla104 ? rev. 1.0.9 10 fxla104 ? low-voltage dual-suppl y 4-bit voltage translator ac characteristics (continued) v cc =1.4v to 1.6v, t a =-40 to 85c symbol parameter v ccb =3.0v to 3.6v v ccb =2.3v to 2.7v v ccb =1.65v to 1.95v v ccb =1.4v to 1.6v v ccb =1.1v to 1.3v units min. max. min. max. min. max min. max. typ. t plh ,t phl a to b 0.5 6.0 0.5 6.5 1.0 7.0 1.0 8.5 7.9 ns b to a 0.6 6.8 0.8 6.9 0.9 7.5 1.0 8.5 6.1 ns t pzl ,t pzh /oe to a, /oe to b 1.7 1.7 1.7 1.7 1.7 s t skew a port, b port (12) 1.0 1.0 1.0 1.0 1.0 ns v cca =1.1v to 1.3v, t a =-40 to 85c symbol parameter v ccb =3.0v to 3.6v v ccb =2.3v to 2.7v v ccb =1.65v to 1.95v v ccb =1.4v to 1.6v v ccb =1.1v to 1.3v units typ. typ. typ. typ. typ. t plh ,t phl a to b 4.6 4.8 5.4 6.2 9.2 ns b to a 6.8 7.0 7.4 7.8 9.1 ns t pzl ,t pzh /oe to a, /oe to b 1.7 1.7 1.7 1.7 1.7 s t skew a port, b port (12) 1.0 1.0 1.0 1.0 1.0 ns note: 12. skew is the variation of propagat ion delay between output signals and applies only to output signals on the same port (a n or b n ) and switching with the same polarity (low-to-high or high-to-low) (see figure 11). skew is guaranteed, but not tested.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fxla104 ? rev. 1.0.9 11 fxla104 ? low-voltage dual-suppl y 4-bit voltage translator maximum data rate (13, 14) t a =-40 to 85c v cca v ccb =3.0v to 3.6v v ccb =2.3v to 2.7v v ccb =1.65v to 1.95v v ccb =1.4v to 1.6v v ccb =1.1v to 1.3v units min. min. min. min. typ. v cca =3.00v to 3.60v 140 120 100 80 40 mbps v cca =2.30v to 2.70v 120 120 100 80 40 mbps v cca =1.65v to 1.95v 100 100 80 60 40 mbps v cca =1.40v to 1.60v 80 80 60 60 40 mbps v cca =1.10v to 1.30v typ. typ. typ. typ. typ. 40 40 40 40 40 mbps notes: 13. maximum data rate is guaranteed, but not tested. 14. maximum data rate is spec ified in megabits per second (see figure 10) . it is equivalent to two times the f-toggle frequency, specified in megahertz. fo r example, 100mbps is equivalent to 50mhz. capacitance symbol parameter conditions t a =+25c typical units c in input capacitance control pin (/oe) v cca =v ccb =gnd 3 pf c i/o input/output capacitance a n v cca =v ccb =3.3v, /oe=v cca 4 pf b n 5 c pd power dissipation capacitance v cca =v ccb =3.3v, v i =0v or v cc , f=10mhz 25 pf
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fxla104 ? rev. 1.0.9 12 fxla104 ? low-voltage dual-suppl y 4-bit voltage translator i/o architecture benefit the fxla104 i/o architecture benefits the end user, beyond level translation, in the following three ways: auto direction without an external direction pin. drive capacitive loads . automatically shifts to a higher current drive mode only during ?dynamic mode? or hl / lh transitions. lower power consumption . automatically shifts to low-power mode during ?static mode? (no transitions), lowering power consumption. the fxla104 does not require a direction pin. instead, the i/o architecture detects input transitions on both side and automatically transfers the data to the corresponding output. for example, for a given channel, if both a and b side are at a static low, the direction has been established as a ? b, and a lh transition occurs on the b port; the fxla104 internal i/o architecture automatically changes direction from a ? b to b ? a. during hl / lh transitions, or ?dynamic mode,? a strong output driver drives the outpu t channel in parallel with a weak output driver. after a typical delay of approximately 10ns ? 50ns, t he strong driver is turned off, leaving the weak driver enabled for hold ing the logic state of the channel. this weak driver is called the ?bus hold.? ?static mode? is when only the bus hold drives the channel. the bus hold can be over ridden in the event of a direction change. the strong driver allows the fxla104 to quickly charge and discharge capacitive transmission lines during dynamic mode. static mode conserves power, where i cc is typically < 5a. bus hold minimum drive current specifies the minimum amount of current the bus hold driver can source/sink. the bus hold minimum drive current (ii hold ) is v cc dependent and guaranteed in the dc electrical tables. the intent is to maintain a valid output state in a static mode , but that can be overridden when an input data transition occurs. bus hold input overdrive drive current specifies the minimum amount of current required (by an external device) to overdrive the bus hold in the event of a direction change. the bus hold overdrive (ii odh , ii odl ) is v cc dependent and guaranteed in the dc electrical tables. dynamic output current the strength of the output driver during lh / hl transitions is referenced on page 8, dynamic output electrical characteristics, i ohd , and i old .
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fxla104 ? rev. 1.0.9 13 fxla104 ? low-voltage dual-suppl y 4-bit voltage translator test diagrams figure 4. test circuit table 1. ac test conditions test input signal output enable control t plh , t phl data pulses 0v t pzl 0v high to low switch t pzh v cci high to low switch table 2. ac load figure 5. waveform for inverting and non-inverting functions notes: 15. input t r = t f = 2.0ns, 10% to 90%. 16. input t r = t f = 2.5ns, 10% to 90%, at v i = 3.0v to 3.6v only. v cc dut c1 r1 test signal v cci v cco gnd data in data out t pxx t pxx v mi v mo v cco c1 r1 1.2v 0.1v 15pf 1m 1.5v 0.1v 15pf 1m 1.8v 0.15v 15pf 1m 2.5v 0.2v 15pf 1m 3.3v 0.3v 15pf 1m
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fxla104 ? rev. 1.0.9 14 fxla104 ? low-voltage dual-suppl y 4-bit voltage translator figure 6. 3-state output low enable time for low voltage logic notes: 17. input t r = t f = 2.0ns, 10% to 90%. 18. input t r = t f = 2.5ns, 10% to 90%, at v i = 3.0v to 3.6v only. figure 7. 3-state output high enable time for low voltage logic notes: 19. input t r = t f = 2.0ns, 10% to 90%. 20. input t r = t f = 2.5ns, 10% to 90%, at v i = 3.0v to 3.6v only. table 3. test measure points symbol v dd v mi (21) v cci /2 v mo v cco /2 v x 0.9 x v cco v y 0.1 x v cco note: 21. v cci =v cca for control pin /oe or v mi (v cca /2).
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fxla104 ? rev. 1.0.9 15 fxla104 ? low-voltage dual-suppl y 4-bit voltage translator rise cco o i l out o i l ohd t v c c t v c c i ? ? + = + %) 80 % 20 ( ) ( ) ( / / figure 8. active output rise time and dynamic output current high fall cco o i l out o i l old t v c c t v c c i ? ? + = + %) 20 % 80 ( ) ( ) ( / / figure 9. active output fall time and dynamic output current low figure 10. maximum data rate figure 11. output skew time note: 22. t skew = (t phlmax ? t phlmin ) or (t plhmax ? t plhmin ) t rise 80% x v cco 20% x v cco v oh v ol v out time t fall 80% x v cco 20% x v cco v ol v oh v out time v cci v cci /2 v cci /2 gnd data in t w maximum data rate, f = 1/t w v cco v mo t skew t skew v mo gnd data output v cco v mo v mo gnd data output
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fxla104 ? rev. 1.0.9 16 fxla104 ? low-voltage dual-suppl y 4-bit voltage translator physical dimensions figure 12. 16-lead, umlp, quad, ultra-thin mlp, 1.8 x 2.6mm package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packagi ng area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . recommended land pattern notes: a. package does not fully conform to jedec standard. b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m, 1994. d. land pattern recommendation is based on fsc design only. e. drawing filename: mkt-umlp16arev4. f. terminal shape may vary according to package supplier, see terminal shape variants. scale : 2x lead option 1 scale : 2x lead option 2 pin#1 ident pin#1 ident package edge top view bottom view 0.10 c 0.08 c 2.60 1.80 0.10 c 2x 2x side view 0.10 c 0.05 0.00 0.10 c a b 0.05 c 0.55 max. 0.40 1 5 9 13 16 2.10 2.90 0.40 0.663 0.563 0.225 1 (15x) (16x) 0.152 0.40 0.60 0.10 0.30 0.50 0.10 terminal shape variants 0.15 0.25 15x pin 1 non-pin 1 0.15 0.25 15x 0.30 0.50 0.15 0.25 0.30 0.50 0.15 0.25 15x 15x supplier 1 supplier 2 pin 1 non-pin 1 a b c seating plane 0.45 0.35 0.55 0.45 0.25 0.15 r0.20
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fxla104 ? rev. 1.0.9 17 fxla104 ? low-voltage dual-suppl y 4-bit voltage translator physical dimensions figure 13. 12-lead, umlp, quad, jedec mo-252 1.8 x 1.8mm package package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packagi ng area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . a b c seating plane recommended land pattern notes: a. package does not fully conform to jedec standard. b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m, 1994. d. land patter n recommendation is based on fsc design only. e. drawing filename: mkt-umlp12arev4. scale : 2x lead option 1 scale : 2x lead option 2 detail a scale : 2x pin#1 ident top view bottom view 0.10 c 0.08 c 0.10 c 2x 2x side view 0.10 c 0.05 0.00 3 6 1 0.10 cab 0.05 c 0.55 max. 12 1.80 1.80 0.40 0.25 0.15 (12x) 0.35 0.45 2.10 2.10 0.40 0.563 (11x) 0.20 (12x) 1 0.152 9 0.588 detail a pin#1 ident (11x) package edge 0.10 0.10 0.45 0.35 0.10
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fxla104 ? rev. 1.0.9 18 fxla104 ? low-voltage dual-suppl y 4-bit voltage translator

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